In many high performance computer processing systems there are multiple memory ports or access paths between a processor and main memory. The use of multiple memory ports or access paths to main memory allows for faster memory access and, hence, faster operation of the processor. Unfortunately, the existence of multiple paths to main memory also introduces two types of memory problems. One type of problem occurs when multiple processors or multiple ports of a single processor attempt to access the same memory location simultaneously. This type of problem is traditionally solved by suspending all memory requests by all ports affected by the conflicting memory access requests until the conflict is resolved.
The second type of problem, referred to as a memory hazard, is well known to those skilled in the art and has been described in Vector Data Logical Usage Conflict Detection, U.S. Pat. No. 4,789,925; Chaining and Hazard Apparatus and Method, U.S. Pat. No. 4,935,849; Chaining and Hazard Apparatus and Method, U.S. Pat. No. 4,969,117; and System for Implementing Multiple Lock Indicators on Synchronous Pended Bus in Multiprocessor Computer System, U.S. Pat. No. 4,949,239.
A memory hazard occurs when a memory reference may happen in an order different than that which the user intended. For example, if a program stores (i.e., writes) a value to a memory location and then loads (i.e., reads) from that same memory location, the correct value must be read. When there are multiple paths between a processor and main memory, memory operations can traverse different paths and may encounter different delays associated with their respective paths. Thus, it is possible that two memory operations issued from the same processor and addressed to the same memory location could arrive at that memory location in a different order than they were issued. If one or both of these memory operations modifies that memory location, then the program could produce erroneous results. The inability to guarantee that memory operations (i.e., store and load instructions) will access a single memory location in the intended order is referred to as a memory hazard. Depending upon the mix of memory operations, a write-after-write hazard, read-after-write hazard, or write-after-read hazard could result.
The problem of memory hazards is encountered when multiple memory operations address the same memory location and at least one of those memory operations is a store. In high performance computer systems with multiple processors accessing main memory over multiple ports in a non-sequential manner, some mechanism must be provided to avoid the memory hazards and insure memory coherency. For purposes of the present invention, memory coherency in a processor with multiple memory ports is achieved when memory operations produce the same results as if there were only one sequential path to main memory.
The prior art provides two general solutions for handling the problem of memory hazards. In the first solution, the processor suspends all memory operations in response to a compiler-detected memory hazard until the memory hazard has been resolved. A second solution uses additional hardware to detect and resolve the memory hazard. For example, one prior art technique teaches using some type of hardware "lock" for each memory location to indicate when that location is in use during a read-modify-write operation and thus ensuring that the read-modify-write operation occurs in the proper order. Another hardware solution uses a conflict resolution hardware network and the odd/even chaining of alternate memory banks within each section of main memory to ensure that memory requests are executed in the order in which they are issued.
Although the prior art techniques are capable of handling memory hazards in processors having multiple memory ports, these techniques rely either on hardware mechanisms to detect and to resolve memory conflicts and memory hazards, or on the suspension of all memory operations during the resolution of memory hazards. Consequently, it would be desirable to provide a method and apparatus for resolving memory hazards in processors having multiple memory ports which minimizes any impact on processor performance while waiting for such memory hazards to clear without requiring additional circuitry to detect the existence of memory hazards.